1. Field of the Invention
The present invention relates generally to an architecture for a power-up reset circuit. More particularly, it relates to an all-digital power-up circuit having advantageous properties, such as an output reset pulse having a predictable width in the face of variances in manufacturing processes, ambient temperature, etc.
2. Background of Related Art
Power-up or power-on reset circuits are generally used to provide a digital reset pulse to circuitry (e.g., processors) when power is first applied to a system and becomes stable. Depending upon the impedance of a particular system and/or the output drive of a particular power supply, power-up reset signal pulses are generally initiated within 1 or so seconds of initial power-up.
Most conventional power-on reset circuits are designed using analog, passive components such as a resistor, a capacitor, and a one shot pulse generator such as a Schmitt-trigger gate. The resistor and capacitor provide a slowly rising voltage level, which at a predetermined level triggers a pulse to be output,from the Schmitt-trigger gate.
In many applications, the conventional analog power-on reset works suitably well. However, a problem arises when it is desired to generate a power-on reset pulse having a specific width. The width of the conventional power-on reset pulse depends heavily on the values of the resistor and the capacitor. Moreover, the width of the output reset pulse varies in response to changes in other parameters as well. For instance, the width of the output reset pulse is subject to, e.g., variations due to process parameters and/or changes in the ambient temperature.
A conventional power-up reset circuit is shown in FIG. 3.
In particular, in FIG. 3, an analog power-up reset circuit includes a resistor 302 and a capacitor 304 in series between power VDD, and ground GND. The node 320 between the resistor 302 and the capacitor 304 is input into an appropriate Schmitt-trigger 306. The output reset pulse RESETN 310 is input to appropriate hardware devices, e.g., ASIC Device 308.
When initially powered-up, the power node VDD rises substantially immediately in voltage from ground level to its powered level, e.g., 5 volts. However, the node 320 is filtered by the resistor 302/capacitor 304 combination, and thus relatively slowly rises in voltage level from ground level to VDD. Once the voltage level at the node 320 rises beyond a predetermined threshold level of an input of said Schmitt-trigger 306, a reset pulse RESETN 310 is output from the Schmitt-trigger 306.
The conventional power-up reset circuit, e.g., as shown in FIG. 3, works well in circuit simulations, particularly when under the assumption that the device supply voltage VDD rises quickly to its powered, maximum level (e.g., 5 volts), and stays there without any glitches. With a proper selection of the appropriate resistor-capacitor (RC) time constant with a proper choice of resistor and capacitor values, the Schmitt-trigger 306 will initially hold the system in reset with a de-active (e.g., LOW logic level) reset pulse RESETN 310, then provide just one reset pulse.
Unfortunately, a conventional power-up reset circuit has two particular problems. Firstly, the width of the output reset pulse RESETN 310 varies with variances in power supplies, e.g., having different power-up rise times. Moreover, the width of the output reset pulse RESETN 310 also varies because of variances in process parameters from device to device during a manufacturing run, requiring looser design standards. Furthermore, changes in the ambient temperature may cause corresponding changes in the RC time constant formed by the resistor 302 and capacitor 304 as well as characteristics of the Schmitt-trigger device 306. Secondly, power interruptions will typically cause the supply voltage to correspondingly drop to O V for short periods of time, causing the internal states of flip-flop latches inside the ASIC device 308 to become unstable, but typically not sufficient enough to cause the RC filter 302, 304 to discharge to cause the output reset pulse RESETN 310 to stay inactive. Consequently, the conventional analog-based power-up reset circuit may occasionally loose track of its own internal states, causing instabilities in the electronic system.
There is a need for an improved power-up reset circuit which outputs a reset pulse having a predictable width which does not vary significantly from device to device in a manufacturing production run, and/or which does not vary significantly due to changes in ambient temperature.